1. Technical Field
The present invention relates to integrated circuits in general, and in particular to a method and apparatus for providing noise immunity to an integrated circuit. Still more particularly, the present invention relates to a method and apparatus for automatically adjusting noise immunity of an integrated circuit.
2. Description of the Prior Art
Among integrated circuit design families, dynamic logic circuits offer significant advantages over their static logic circuit counterparts, particularly in performance and chip area requirements. Therefore, it is usually desirable to use dynamic logic circuits to implement as much of the logic function of an integrated circuit design as possible.
Generally speaking, dynamic logic circuits use a stored charge to represent a logic state. In operation, the charge is usually stored at a storage node during a precharge phase, and the charge is then conditionally discharged during an evaluation phase. However, the stored charge can be accidentally degraded due to various leakage or noise problems such as charge sharing, capacitive coupling from adjacent signals, sub-threshold conduction of n-channel pull-down transistors, and conduction through n-channel pull-down transistors due to noise on inputs. If a sufficient amount of the charge stored on the storage node is lost due to one or more of the above-mentioned problems, the output of the dynamic logic circuit will transition to an unintended state. This error can propagate and cause erroneous results throughout the entire integrated circuit design.
One method that can be used to avoid noise-induced failures is to provide some sort of "weak" feedback mechanism to maintain the stored charge at the storage node. However, the charge supplied by the weak feedback mechanism adversely affects the performance of the circuit. This is because, during the evaluation phase, the n-channel pull-down transistor network not only has to discharge the stored charge at the precharge node but also has to counter the small amount of charge supplied by the feedback mechanism. As a result, the amount of time to discharge the precharge node is increased. In view of such, a circuit designer must make a trade-off between the performance impact from sizing the feedback mechanism too large and the risk of not providing enough feedback by sizing the feedback mechanism too small. However, in most cases, such trade-offs are not even an option. For example, for reliability reasons, integrated circuits are often subjected to high-voltage and high-temperature burn-in tests in order to stress the design to accelerate early failures. Because high voltages and high temperatures can aggravate most of the above-mentioned leakage and noise problems, the circuit designer must design-in a greater amount of feedback than is required for normal operation in order to ensure that the integrated circuit will remain operational under the burn-in conditions. The additional amount of feedback can affect performance in stress conditions when high performance is not required as well as in normal operational conditions when performance is paramount.